NSCC Signs MoU with RiST

On 20 June 2016, the Research Organization for Information Science and Technology (RIST) and the National Supercomputing Centre Singapore (NSCC) signed a Memorandum of Understanding (MOU) expressing interest to conduct bilateral exchange of information.

RIST is a Japanese non-profit public-service organisation working for the development and utilisation of computational science and technology to support highly information-oriented societies. It currently oversees the awarding process of K computer general use category project proposals, High Performance Computing Infrastructure (HPCI) system project proposals and user services and technical support.

In accordance with the MOU, RIST and NSCC will schedule regular meetings for the exchange of information between both organisations on activities relating to the areas of:

  1. promotion of shared use of supercomputers,
  2. supercomputer user support and human resource development, and
  3. exploring the possibility of co-operation related to these activities.

Through these activities, both organisations aim to contribute to the HPC community in each country as well as collaboration between two communities.


20 June 2016

At ISC2016 Supercomputing Conference in Frankfurt

A/Prof. Tan Tin Wee, Director, NSCC (left)

Dr. Motoi Okuda, Deputy Head of Kobe center, RIST (right)

Post-Alpha Testbed Town Hall Meetings

CAD-IT ANSYS Convergence 2016DSC_0177NSCC is organising a series of town hall meetings as a follow-up to the Alpha Testbed. We will update the users of the status and explain the changes to be implemented post Alpha Testbed. We will also seek input from our users based on their experience with the Alpha Testbed. All users are encouraged to participate in the meeting near you.

Date/Time Location
Tue Jun14 10:00 AM Fusionopolis, MPH 2, Level 1, Tower A, Innovis
Tue Jun14 2:00 PM NTU, SPMS COMP LAB 1 (SPMS-MAS-03-02)
Wed Jun15 10:00 AM Biopolis, Creation Theatre, Level 4, Matrix
Wed Jun15 2:00 PM NUS, CIT Auditorium, L2 Computer Centre

Workshop: Optimisation Techniques, May 25, A*STAR


Optimisation Techniques

Part 1. General Overview

  • Optimization process: guidance, tips and tricks
  • How to decide which optimization techniques to focus on
  • Performance characteristics of the Haswell architecture

Part 2. Compiler optimization

  • Optimization Flags
  • OpenMP compilation
  • Optimized libraries
  • Precision and reproducibility
  • Options for correctness checking and debugging
  • Options for source code optimization reports (Intel compiler)
  • Hands-on session

Part 3. MPI optimization

  • Gathering communication statistics
  • Improving MPI communication
  • Process & Thread placement
  • Hands-on session

Part 4. Advanced topics

  • Profile guided optimization (Intel compiler)
  • Auto-parallelization (Intel compiler)
  • Hands-on session

This workshop is fully subscribed. Details can be found on the Workshop website.